(1) Field of the Invention
This invention relates to integrated circuit semiconductor devices, and more particularly to a method for making bipolar transistors having improved emitters in bipolar/CMOS devices. This novel method results in bipolar transistors having emitters with shallower junction depths and better process control of the junction depth. These shallower junction depths are useful for submicrometer high-speed BiCMOS circuits in which the bipolar transistor performance is improved, for example, by increasing the breakdown (punchthrough) voltage, increasing the cutoff frequency, while maintaining a reasonable current gain.
(2) Description of the Prior Art
BiCMOS circuits are formed by integrating bipolar transistors and complementary metal on silicon (CMOS) field effect transistor (FET) devices on the same silicon chip. The CMOS devices provide low power and high density for digital applications, while bipolar transistors (current switch) require high power consumption and provide higher off-chip drive currents and lower logic swings. Many of the application-specific integrated circuits (ASIC) take advantage of these opposing properties by integrating the bipolar transistors and FET devices on the same silicon chip.
However, one problem on integrating the two devices on the same chip is optimizing the electrical characteristics of one device without adversely affecting the electrical characteristics of the other device. In one approach, to save process steps it is desirable to form the FET gate electrodes and concurrently to form the doped polysilicon emitter for the bipolar transistor. It is necessary to use a rapid thermal anneal (RTA) to activate the dopant implant for the FET source/drain contacts for low contact resistance after forming the FET gate electrodes and the bipolar emitter. However, this RTA makes it difficult to control the shallow diffused emitter junction depth to achieve a high-performance bipolar transistor.
Several methods for making bipolar transistors in BICMOS circuits are described in the literature. For example, in U.S. Pat. No. 5,773,340 to Kumauchi et al., a phosphorus-doped amorphous silicon layer is deposited and annealed to convert the amorphous silicon into a polysilicon for doping the bipolar emitter. The phosphorus present in the amorphous silicon is diffused into the bipolar active base region, followed by a high-temperature/short-time annealing to activate the impurity dopants for the source/drain regions of the MOS-FETs. In the invention U.S. Pat. No. 5,874,333 to Chang et al. a method is described for forming a doped polysilicon layer having a less rough upper layer. This is achieved by depositing the polysilicon layer at a high temperature (about 630.degree. C.) and, without interrupting the deposition process, the temperature is ramped down to 560.degree. C. to provide a smooth surface having minimal grain growth. In U.S. Pat. No. 5,953,600 to Gris the FETs are formed prior to forming the bipolar transistor. This allows the source/drain contacts to be activated by RTA prior to forming the shallow emitters for the bipolar transistor. However, this process requires additional process steps. In U.S. Pat. No. 5,028,557 to Tsai et al. a reverse self-aligned BICMOS circuit is described in which polysilicon source/drain contacts for the FETs are formed by out-diffusion and the extrinsic base for the bipolar transistor are made prior to forming the polysilicon emitter self-aligned to the extrinsic base (polysilicon) contacts. In U.S. Pat. No. 5,466,615 to Tsai a protective block layer is formed over the substrate where the FET gate electrode and bipolar transistor emitter areas are to be formed. This patent also uses a reversed self-aligned process to form the BiCMOS circuit. In U.S. Pat. No. 6,004,855 to Pollock et al. a high-performance bipolar transistor structure is described in which an interdigitated collector is made self-aligned to the emitter over the active base area. The invention does not address the integration of this bipolar transistor with CMOS devices.
However, there is still a need in the industry to provide a process for making BiCMOS circuits having bipolar transistors with shallower diffused junctions while being able to accurately control the emitter junction depth (fine tune) without adversely affecting electrical characteristics of the other devices on the chip. It is also important to achieve this goal while maintaining a cost-effective manufacturing process for making the BiCMOS circuits.